MuxDemux

Many inputs, one decision. One decision, many actions.

Sensors ----+ +---- Motor A Memory ----+--> [ MUX ] --> [ BRAIN ] --> [ DEMUX ] --+---- Motor B Context ----+ select decide route +---- Motor C Signals ----+ +---- Motor D

The Multiplexer

⨯ What It Does

A multiplexer selects one of many inputs and forwards it to a single output line. Select lines act as the address, choosing which input passes through. A 2:1 mux uses 1 select line. A 4:1 uses 2. An 8:1 uses 3. The pattern: n select lines address 2n inputs.

⇄ The Demultiplexer

The inverse operation. One input, routed to one of many outputs based on select lines. Where a mux concentrates, a demux distributes. Together they form the fundamental routing fabric of every digital system ever built.

Scaling: From Gates to Processors

2:1 MUX — 1 select line 4:1 MUX — 2 select lines 8:1 MUX — 3 select lines 16:1 MUX — 4 select lines 2n:1 — n select lines

⚙ Inside the ALU

The arithmetic logic unit uses multiplexers to select operands from registers, choose which operation to execute (add, subtract, AND, OR), and route results back to the register file. Every instruction cycle is a mux decision.

■ Building n-bit

A 32-bit processor cascades mux layers for each bit position. Shannon proved in 1937 that any Boolean function decomposes into a hierarchy of multiplexers. His expansion theorem is the mathematical bedrock of all digital design.

Three Domains, One Pattern

⚡ Silicon

Transistors switch voltage levels. Select lines address input channels. Nanosecond decisions route data through billions of gates. The CPU is a mux/demux machine.

🧠 Biology

The thalamus multiplexes sensory streams — vision, sound, touch, pain — into focused attention. Motor cortex demultiplexes intent into specific muscle groups. Attention is biological multiplexing.

🤖 Intelligence

AI agents multiplex heterogeneous inputs — memory, context, tools, observations — into a single decision point. They demultiplex that decision into parallel actions: API calls, code, messages, delegation. Orchestration is applied mux/demux theory.

Building From Nothing: NAND to Mux

📖 The Elements of Computing Systems

In the celebrated Nand2Tetris course by Noam Nisan and Shimon Schocken, students build an entire computer from a single primitive: the NAND gate. The course proves that NAND is functionally complete — any Boolean function can be built from NAND alone. The first project starts with NAND and ends with Mux8Way16 and DMux8Way. By chapter 5, you have a working CPU.

The Primitive: NAND

NAND (Not-AND) is the only gate given to you. Everything else is built from it.

NAND Truth Table From NAND, build everything: A B | out 0 0 | 1 NOT(x) = NAND(x, x) [1 gate] 0 1 | 1 AND(a,b) = NOT(NAND(a,b)) [2 gates] 1 0 | 1 OR(a,b) = NAND(NOT(a), NOT(b)) [3 gates] 1 1 | 0 XOR(a,b) = 4 NAND gates

Mux from 4 NAND Gates

The multiplexer — the selector at the heart of every processor — needs just 4 NAND gates:

Boolean: out = (a AND NOT sel) OR (b AND sel) NAND construction (4 gates): w1 = NAND(sel, sel) ← NOT sel w2 = NAND(a, w1) ← NAND(a, NOT sel) w3 = NAND(b, sel) ← NAND(b, sel) out = NAND(w2, w3) ← final output +--------+ sel ----+--->| NAND 1 |---w1 | +--------+ | +--------+ a ------+--->| NAND 2 |---w2--+ | +--------+ | +--------+ | +->| NAND 4 |--->out | +--------+ | +--------+ b ------+--->| NAND 3 |---w3--+ +--------+

DMux from 5 NAND Gates

The demultiplexer routes one input to one of two outputs. The inverse of Mux:

Boolean: a = in AND NOT sel b = in AND sel NAND construction (5 gates): w1 = NAND(sel, sel) ← NOT sel w2 = NAND(in, w1) ← NAND(in, NOT sel) a = NAND(w2, w2) ← AND(in, NOT sel) w3 = NAND(in, sel) ← NAND(in, sel) b = NAND(w3, w3) ← AND(in, sel) If sel=0: a=in, b=0 If sel=1: a=0, b=in

The Nand2Tetris HDL

Mux.hdl

CHIP Mux { IN a, b, sel; OUT out; PARTS: Not(in=sel, out=notSel); And(a=a, b=notSel, out=aNotSel); And(a=b, b=sel, out=bSel); Or(a=aNotSel, b=bSel, out=out); }

DMux.hdl

CHIP DMux { IN in, sel; OUT a, b; PARTS: Not(in=sel, out=notSel); And(a=in, b=notSel, out=a); And(a=in, b=sel, out=b); }

Scaling Up: The Tree Pattern

Multi-way muxes compose as binary trees. Each level adds one select bit, doubling the input count:

Mux4Way16 (2 select bits, 4 inputs of 16 bits each): Mux16(a, b, sel[0]) → ab Mux16(ab, cd, sel[1]) → out Mux16(c, d, sel[0]) → cd / Mux8Way16 (3 select bits, 8 inputs): Mux4Way16(a,b,c,d, sel[0..1]) → abcd Mux16(abcd, efgh, sel[2]) → out Mux4Way16(e,f,g,h, sel[0..1]) → efgh / DMux mirrors this in reverse — one input fans out through the tree.
Not — 1 NAND And — 2 NANDs Or — 3 NANDs Mux — 4 NANDs DMux — 5 NANDs Mux16 — 64 NANDs Mux4Way16 — 192 NANDs Mux8Way16 — 448 NANDs

Inside the ALU: Mux as Decision Maker

The Hack ALU from Nand2Tetris uses six control bits, each driving a Mux16 to conditionally transform the inputs. This elegant cascade lets one circuit compute 18 different functions:

x,y (16-bit inputs) 6 control bits: zx, nx, zy, ny, f, no if zx: x = 0 → Mux16(x, 0, sel=zx) if nx: x = !x → Mux16(x, Not16(x), sel=nx) if zy: y = 0 → Mux16(y, 0, sel=zy) if ny: y = !y → Mux16(y, Not16(y), sel=ny) if f: out = x+y → Mux16(And16(x,y), Add16(x,y), sel=f) else: out = x&y if no: out = !out → Mux16(out, Not16(out), sel=no) Result: 0, 1, -1, x, y, !x, !y, -x, -y, x+1, y+1, x-1, y-1, x+y, x-y, y-x, x&y, x|y

Timeline

1937

Claude Shannon proves Boolean algebra can implement any logical function in electrical circuits. His expansion theorem shows every function is a mux tree.

1950s

Telephone switching networks become the first industrial-scale mux/demux systems, routing thousands of calls through shared copper.

1970s

Integrated circuits put multiplexers on silicon. The 74151 (8:1 mux) and 74138 (3:8 demux) become building blocks of early microcomputers.

2020s

AI agent orchestration applies the pattern at a new level. Multiple models, multiple tools, multiple knowledge sources — multiplexed into decisions, demultiplexed into coordinated action across machines and networks.